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Features
ARM7TDMITM ARM(R) Thumb(R) Processor Core Two 16-bit Fixed-point OakDSPCore(R) Cores 256 x 32-bit Boot ROM 88K Bytes of Integrated Fast RAM for Each DSP Flexible External Bus Interface with Programmable Chip Selects Dual Codec Interface Multi-level Priority, Individually Maskable, Vectored Interrupt Controller Three 16-bit Timer/Counters Additional Watchdog Timer Two USARTs with FIFO and Modem Control Lines Industry Standard Serial Peripheral Interface (SPI) Up to 23 General-purpose I/O Pins On-chip DRAM Controller JTAG Debug Interface Software Development Suites Available for ARM7TDMI and OakDSPCore Supported by a Wide Range of Ready-to-use Application Software, including Multitasking Operating System, Networking, Modems, and Voice-processing Functions * Available in 160-lead PQFP Package * 3.3V Power Supply
* * * * * * * * * * * * * * * *
Description
The Atmel AT75C310 Smart Internet Appliance Processor (SIAP) is a high-performance processor specially designed for Internet appliance applications, such as Internet telephony (Voice over Internet Protocol - VoIP). The AT75C310 is built around an ARM7TDMI microcontroller core running at 20 MIPS with two DSP co-processors running at 40 MIPS each - all three processors delivering unmatched performance for low power consumption. In a typical standalone VoIP phone, one DSP handles the voice-processing functions (voice compression, acoustic echo cancellation, etc.), while the other one deals with the telephony functions (dialing, line echo cancellation, callerID detection, high-speed modem, etc.). In such an application, the power of the ARM7TDMI allows it to run the VoIP protocol stack as well as all the system control tasks. Atmel provides the AT75C310 with three levels of software modules: * a special port of the Linux kernel as the proposed operating system * a comprehensive set of tunable DSP algorithms for modems and voice processing, specially tailored to be run by the DSP subsystems * a broad range of application-level software modules such as H323 telephony or POP-3/SMTP e-mail services
Smart Internet Appliance Processor - Electrical and Mechanical Characteristics AT75C310
Rev. 1370A-07/00
1
Absolute Maximum Ratings*
Operating Temperature (Commercial).............0C to +70C Voltage on Any Input Pin with Respect to Ground-..................................0.5V to +4.0V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Maximum Operating Voltage..........................................4.6V
DC Characteristics
Symbol Parameter DC Supply Ambient Temperature Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Condition Min 3.0 0 Typ 3.3 Max 3.6 70 0.3 x VDD 3.6 0.1 Units V C V V V V
VDD
TA VIL VIH VOL VOH
VDD = 3.0V to 3.6V VDD = 3.0V to 3.6V
IOL = 0.8 mA, VDD = 3.3V IOH = 0.8 mA, VDD = 3.3V
-0.5 0.7 x VDD
VDD - 0.1
AC Characteristics
Conditions
The values are for full temperature range and worst-case process.
Environment Constraints
The output delays are valid for a capacitive load of 10 pF, as shown in Figure 1. Figure 1. Output/Bidir Pad Capacitive Load
CL = 10 pF PAD
2
AT75C310
AT75C310
Memory Timing Waveforms
Figure 2. DRAM Read Cycle (Single Read)
tRC tRAS NRASx tCSH tRCD NCASx tRSH tCAS tCRP tRP
tASR A
tRAH
tASC
tCAH
NDOE tCAC tOEA tAA tRAC D tOHO
Table 1. DRAM Read Cycle (Single Read) Timings
Symbol tRC tRAS tRP tCSH tCRP tRCD tRSH tCAS tASR tRAH tASC tCAH tCAC tOEA tAA tRAC tOHO Parameter Read or Write Cycle Time RAS Pulse Width RAS Precharge Time CAS Hold Time CAS to RAS Precharge Time RAS to CAS Delay Time RAS Hold Time CAS Pulse Width Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time Access Time from CAS Access Time from NDOE Access Time from Column Address Access Time from RAS Data Hold from NDOE Min (ns) 125.0 82.0 42.0 61.0 49.0 41.0 29.0 20.0 1.0 22.0 15.0 21.0 - - - - 0 22.0 34.0 38.0 63.0 - Max (ns) - - - - - - - -
3
Figure 3. DRAM Read Cycle (Burst Read)
NRASx tCPRH tCSH tRCD NCASx tCAS tCP tCAS
tASR A
tRAH
tASC
tCAH
tASC
tCAH
NDOE tCAC tOEA tAA tRAC D tOHO tCPA tDOH tAA tCAC
Table 2. DRAM Read Cycle (Burst Read) Timings
Symbol tCPRH tCSH tRCD tCAS tCP tASR tRAH tASC tCAH tCAC tOEA tAA tRAC tCPA tOHO tDOH Parameter RAS Hold Time from CAS Precharge CAS Hold Time RAS to CAS Delay Time CAS Pulse Width CAS Precharge Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time Access Time from CAS Access Time from NDOE Access Time from Column Address Access Time from RAS Access Time from CAS Precharge Data Hold from NDOE Data Hold from CAS Low Min (ns) 48.0 61.0 41.0 20.0 19.0 1.5 22.0 15.0 21.0 - - - - - 0 0 22.0 34.0 38.0 63.0 43.0 - - Max (ns) - - - - -
4
AT75C310
AT75C310
Figure 4. DRAM Write Cycle (Single Write)
tRC tRAS NRASx tCSH tRCD NCASx tRSH tCAS tCRP tRP
tASR A
tRAH
tASC
tCAH
tWCS NDWE
tWCH
tDS D
tDH
Table 3. DRAM Write Cycle (Single Write) Timings
Symbol tRC tRAS tRP tCSH tCRP tRCD tRSH tCAS tASR tRAH tASC tCAH tWCS tWCH tDS tDH Parameter Read or Write Cycle Time RAS Pulse Width RAS Precharge Time CAS Hold Time CAS to RAS Precharge Time RAS to CAS Delay Time RAS Hold Time CAS Pulse Width Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time Write Command Setup Time Write Command Hold Time Data Setup Time Data Hold Time Min (ns) 125.0 82.0 42.0 61.0 49.0 41.0 29.0 20.0 1.5 22.0 15.0 21.0 18.0 21.0 8.0 21.0 Max (ns) - - - - - - - - - - - - - - - -
5
Figure 5. DRAM Refresh Cycle
tRC tRP NRASx tRPC tCP NCASx tCSR tCHR tCRP tRAS tRP
tWRP NDWE
tWRH
Table 4. DRAM Refresh Cycle Timings
Symbol tRC tRAS tRP tCP tRPC tCSR tCHR tCRP tWRP tWRH Parameter Cycle Time RAS Pulse Width RAS Precharge Time CAS Precharge Time RAS Precharge before CAS CAS Setup before RAS CAS Hold after RAS CAS to RAS Precharge Time Write Enable Setup Time (Refresh Cycle) Write Enable Hold Time (Refresh Cycle) Min (ns) 125.0 82.0 42.0 19.0 33.0 48.0 32.0 49.0 91.0 32.0 Max (ns) - - - - - - - - - -
6
AT75C310
AT75C310
Figure 6. Static Memory Read Cycle (Zero Wait State)
tCSLCSH NCEx
A
tRLRH NSOE (Standard Read Mode)
NSOE (Early Read Mode)
NWEx (Byte Select Mode) tRLDV1 tCSLDV tRLDV 2 tAVDV tBSLDV D tRHDH tRHCSH tRHAH tRHBSH
Table 5. Static Memory Read Cycle (Zero Wait State) Timings
Symbol tCSLCSH tRLRH tRLDV1 tRLDV2 tCSLDV tAVDV tBSLDV tRHCSH tRHAH tRHBSH tRHDH Parameter Chip Select Low to Chip Select High Time Read Strobe Low to Read Strobe High Time Read Strobe Low to Data Valid Time - Standard Read Mode Read Strobe Low to Data Valid Time - Early Read Mode Chip Select Low to Data Valid Address Valid to Data Valid Byte Select Low to Data Valid Read Strobe High to Chip Select High Address Hold after Read Strobe High Read Strobe High to Byte Select High Data Hold after Read Strobe High Min (ns) 40.0 19.0 - - - - - 0 0 0 0 Max (ns) - - 6.0 27.0 25.0 24.0 26.0 - - - -
7
Figure 7. Static Memory Write Cycle (Zero Wait State)
tCSLCSH NCEx
A
NWEx (Byte Select Mode) tCSLWL tAVWL tBSLWL tWLWH tWHCSH tWHAH tWHBSH
NWR/NWEx (Byte Write Mode)
tDSUWH D
tWHDH
Table 6. Static Memory Write Cycle (Zero Wait State) Timings
Symbol tCSLCSH tCSLWL tAVWL tBSLWL tWHCSH tWHAH tWHBSH tWLWH tDSUWH tWHDH Parameter Chip Select Low to Chip Select High Time Chip Select Low to Write Stobe Low Time Address Valid to Write Strobe Low Time Byte Select Low to Write Strobe Low Time Write Strobe High to Chip Select High Time Address Hold Time after Write Strobe High Write Strobe High to Byte Strobe High Time Write Strobe Low to Write Strobe High Time Data Setup Time before Write Strobe High Data Hold Time after Write Strobe High Min (ns) 40.0 18.0 17.0 19.0 3.0 4.0 0 17.0 13.0 3.0 Max (ns) - - - - - - - - - -
8
AT75C310
AT75C310
Figure 8. Static Memory Write Cycle (One Wait State)
tCSLCSH NCEx
A
NWEx (Byte Select Mode) tCSLWL tAVWL tBSLWL tWLWH tWHCSH tWHAH tWHBSH
NWR/NWEx (Byte Write Mode)
tDSUWH D
tWHDH
Table 7. Static Memory Write Cycle (One Wait State) Timings
Symbol tCSLCSH tCSLWL tAVWL tBSLWL tWHCSH tWHAH tWHBSH tWLWH tDSUWH Parameter Chip Select Low to Chip Select High Time Chip Select Low to Write Stobe Low Time Address Valid to Write Strobe Low Time Byte Select Low to Write Strobe Low Time Write Strobe High to Chip Select High Time Address Hold Time after Write Strobe High Write Strobe High to Byte Strobe High Time Write Strobe Low to Write Strobe High Time Data Setup Time before Write Strobe High Min (ns) 82.0 20.0 19.0 20.0 19.0 20.0 19.0 40.0 38.0 Max (ns) - - - - - - - - - -
tWHDH Data Hold Time after Write Strobe High 20.0 Note: Additional wait states will extend the tWLWH and tDSUWH values by one clock period per wait state.
9
Figure 9. Static Memory Write Cycle (LCD Mode, Two Wait States)
tCSLCSH NCE3
tAVCSL A tAVWL tWLWH NWR/NWEx tDVCSH tDVWH D tCSHDH tWHDH
tCSHAH
tWHAH
Table 8. Static Memory Write Cycle (LCD Mode, Two Wait States Timings
Symbol tCSLCSH tAVCSL tAVWL tCSHAH tWHAH tWLWH tDVCSH tDVWH tCSHDH tWHDH Parameter Chip Select Low to Chip Select High Time Address Valid to Chip Select Low Time Address Valid to Write Strobe Low Time Address Hold Time after Chip Select High Address Hold Time after Write Strobe High Write Strobe Low to Write Strobe High Time Data Setup Time before Chip Select High Data Setup Time before Write Strobe High Data Hold Time after Write Chip Select High Data Hold Time after Write Strobe High Min (ns) 82.0 18.0 19.0 21.0 20.0 81.0 79.0 79.0 21.0 20.0 Max (ns) - - - - - - - - - -
10
AT75C310
AT75C310
Figure 10. Static Memory Read Cycle (LCD Mode, Two Wait States)
tCSLCSH NCE3
tAVCSL A
tCSHAH
tRLRH NSOE (Standard Read Mode)
NSOE (Early Read Mode) tRLDV1 tCSLDV tAVDV tRLDV2 D tRHDH tCSHDH tRHAH
Table 9. Static Memory Read Cycle (LCD Mode, Two Wait States) Timings
Symbol tCSLCSH tAVCSL tCSHAH tRLRH tRLDV1 tRLDV2 tCSLDV tAVDV tRHAH tRHDH tCSHDH Parameter Chip Select Low to Chip Select High Time Address Valid to Chip Select Low Address Hold after Chip Select High Read Strobe Low to Read Strobe High Time Read Strobe Low to Data Valid Time - Standard Read Mode Read Strobe Low to Data Valid Time - Early Read Mode Chip Select Low to Data Valid Address Valid to Data Valid Address Hold after Read Strobe High Data Hold after Read Strobe High Data Hold after Chip Select High Min (ns) 82.0 18.0 21.0 102.0 - - - - 1.0 0 18.0 89.0 110.0 88.0 107.0 - - - Max (ns) - - -
11
External Bus Master Timing
Figure 11. External Bus Master
NREQ
NGNT
tGLADCZ Address, Data & Control
tGHADC
Table 10. External Bus Master Timings
Symbol tGLADCZ tGHADC Parameter NGNT Low to Address, Data & Control Float NGNT High to Address, Data & Control Driven Min (ns) 2.0 0 Max (ns) - -
12
AT75C310
AT75C310
Codec Timing Waveforms
Figure 12. FS and SCLK as Outputs
tSCLK SSCLK
FS tFSV tFSH
STX tSTXV
SRX tSRXS tRSXH
Table 11. FS and SCLK as Outputs Timings
Symbol tFSV Parameter FS Valid after TX Edge of SSCLK (Long PCM Type) FS Valid after TX Edge of SSCLK (All Other Types) FS Output Hold after Last RX Edge of SSCLK (Long PCM) tFSH FS Output Hold after Last RX Edge of SSCLK (All Other Types) STX Valid after TX Edge of SSCLK SRX Setup before RX Edge of SSCLK SRX Hold after RX Edge of SSCLK Min (ns) - - 49.0 25.0 22.0 50.0 0 Max (ns) 75.0 50.0 - - 25.0 - - 6375.0
tSTXV tSRXS tRSXH tSCLK Note:
SSCLK Generated Period 100.0 All timings based on worst-case conditions of Codec A or B interface and so apply to both.
13
Figure 13. FS and SCLK as Inputs
tFSH SSCLK tSCLK
FS tFSS
STX tSTXV
SRX tSRXS tRSXH
Table 12. FS and SCLK as Inputs Timings
Symbol tFSS tFSH tSTXV tSRXS tRSXH tSCLK Parameter FS Setup before RX Edge of SSCLK FS Hold after First RX Edge of SSCLK STX Valid after TX Edge of SSCLK SRX Setup before RX Edge of SSCLK SRX Hold after RX Edge of SSCLK SSCLK Input Period Min (ns) 75.0 0 50.0 25.0 25.0 200.0 Max (ns) - - 80.0 - - -
14
AT75C310
AT75C310
Packaging Information
Figure 14. SQFP Package Drawing
1
C C 1
Table 13. Package Dimensions for 160-lead SQFP Package (mm)
Symbol c c1 L L1 R2 R1 S 0.13 0.13 0.4 Min 0.11 0.11 0.65 0.15 0.88 1.60 REF 0.3 Nom Max 0.23 0.19 1.03 Symbol A A1 A2 b b1 D D1 E 0.25 0.1 E1 e ddd Min 4.10 0.25 3.20 0.29 0.29 0.35 31.20 28.00 31.20 28.00 0.65 0.12 3.40 0.50 3.60 0.45 0.41 Nom Max
Tolerances of Form and Position
aaa ccc
Thermal Resistance Thermal Resistance = 33C/W
15
Ordering Information
Speed (MHz) 20 Power Supply 3.3V Ordering Code AT75C310-Q160 Package PQFP160 Operation Range Commercial (0 to 70C)
16
AT75C310
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(c) Atmel Corporation 2000. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life suppor t devices or systems. Marks bearing (R) and/or TM are registered trademarks and trademarks of Atmel Corporation. ARM, Thumb and ARM Powered are registered trademarks of ARM Limited. ARM7TDMI is a trademark of ARM Ltd. OakDSPCore is a registered trademark of DSP Group, Inc. Terms and product names in this document may be trademarks of others.
Printed on recycled paper.
1370A-07/00/0M

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